(a) Field of the Invention
The present invention relates to a plasma display panel (PDP). More specifically, the present invention relates to an address data processing device and method for a PDP, and a recording medium for storing a program which includes a method for effectively storing subfield data in a frame memory to generate address data.
(b) Description of the Related Art
A PDP has a plurality of discharge cells arranged in a matrix format, which are configured to selectively emit light, thereby restoring original images using input electrical signals that contain image data.
The PDP has a gray display function for operating as a color display element, and uses a gray realization method for dividing a single field into a plurality of subfields and control them by a time-division rule.
Each subfield has an address interval and a sustain interval. Data for each pixel are transmitted to corresponding scan electrode and address electrode to selectively discharge or erase each cell in the address interval. In the sustain interval, the data for each pixel are maintained, thereby realizing the gray (i.e., gray level).
One of the generally used gray representation methods is an address display separation (ADS) method for completely separating the address interval and the sustain interval.
In the ADS driving method, only the intensity of radiation of the sustain interval is controlled to represent gray of the PDP, and gray representation (levels of from 0 to 255) of RGB video data is performed using ten to sixteen subfields within a single frame.
To display the RGB video data as PDP address data, the video data need to be converted to subfield data. For example, for the case of representing the gray of red 149, the values converted into subfield data using twelve subfields are shown in Table 1.
TABLE 1SFSFSFSFSFSFSFSFSFSFSFSFSubfields01234567891011Weights1246810132132435363Subfield101110110110data
The subfield data generated for gray representation are arranged as address data for driving the PDP. To drive the PDP, the subfield data are stored in a frame memory.
FIG. 1 shows a block diagram of a conventional address data processor in the PDP.
As shown, the conventional address data processor uses six first input first output (FIFO) memories 11 through 16 to receive RGB video data. The memories 11 and 12 receive red (RED) even and odd data and output them, the memories 13 and 14 receive green (GRN) even and odd data and output them, and the memories 15 and 16 receive blue (BLU) even and odd data and output them.
For example, when the conventional PDP has a high definition (HD) level with a resolution of 1,366×768, the FIFO memories each output 8-bit video data.
Six subfield data generators 21 through 26 receive the RGB video data output from the six FIFO memories 11 through 16, respectively, generate subfield data for representing corresponding grays, and output the subfield data. In the case of using twelve subfields, the subfield data generators 21 through 26 each generate 12-bit subfield data for a corresponding cell, and output them as serial outputs.
The 12-bit subfield data outputs generated by the six subfield data generators 21 through 26 each relate to on/off states of the twelve subfields on the gray of a cell. Each of the 12-bit subfield data outputs is data arranged in series with respect to time.
In order to perform an address operation of the PDP, the subfield data of all the cells on a single horizontal line in the same time frame are to be output in parallel, and accordingly, six subfield matrices 31 through 36 receive the subfield data output by the six subfield data generators 21 through 26 into 16 neighboring cells, convert them into 16-bit parallel subfield data, and output them.
In this instance, since the two subfield matrices 21 and 22 respectively represent subfield data of sixteen neighboring cells corresponding to the red video data, and indicate even and odd data, when the respective 16-bit subfield data output by the two subfield matrices 21 and 22 are concatenated by using a concatenator 41, the red subfield data of the thirty-two cells, that is, 32-bit subfield data, are generated and output.
In the same manner, the green subfield data of thirty-two cells and the blue subfield data of thirty-two cells are generated and output, respectively, using the two subfield matrices 23 and 24 and a concatenator 43, and using the two subfield matrices 25 and 26 and a concatenator 45.
The respective 32-bit subfield data generated through the concatenators 41, 43, and 45 are stored in the corresponding frame memories 61 through 66 through the data buffers 51, 53, and 55, respectively. The frame memory 61 and 62 store the red subfield data, the frame memories 63 and 64 store the green subfield data, and the frame memories 65 and 66 store the blue subfield data.
Three subfield data arrangers 71, 73, and 75 receive the subfield data stored in the frame memories through the data buffers 51, 53 and 55, respectively, arrange them as data for per-subfield addressing (i.e., address data for each subfield), and output arranged data so as to represent gray on the PDP. That is, the subfield data arranger 71 receives the red subfield data stored in the frame memories 61 and 62 through the data buffer 51, arranges them, and outputs red address data; the subfield data arranger 73 receives the green subfield data stored in the frame memories 63 and 64 through the data buffer 53, arranges them, and outputs green address data; and the subfield data arranger 75 receives the blue subfield data stored in the frame memories 65 and 66 through the data buffer 55, arranges them, and outputs blue address data.
Regarding using two frame memories for the RGB data, the input video data of the (N−1)th frame are converted into subfield data, the converted subfield data are stored in a single frame memory, the subfield data of the (N−1)th frame stored in the corresponding frame memory are read at the start point of the Nth frame, and they are arranged to generate address data. In this instance, another frame memory is used because the input video data of the Nth frame are to be converted into subfield data and stored while the corresponding frame memory reads the subfield data of the (N−1)th frame. In other words, two frame memories are used since the operation of reading the subfield data of the (N−1)th frame and the operation of storing the subfield data of the Nth frame are concurrently performed in the Nth frame.
A use of six frame memories for processing the HD data is described below.
A high clock frequency should be used for a frame memory for storing video data because of the huge amount of video data converted into subfield data in the HD level PDP. However, a lower clock frequency may be used with an increased number of frame memories because of the limitations in the available clock frequencies. Also, since video data of a single horizontal line cannot be processed during a single horizontal sync at a lower clock frequency, the process is divided into respective RGB processes. The RGB process for each of the red, green and blue color components has even and odd processes. Therefore, the RGB video data are processed using six parallel processes.
It can be seen in FIGS. 1 and 2 that rising edges of the clock signal CLK are used to access the frame memories 61 through 66 through the data buffers 51, 53, and 55. In other words, the 32-bit subfield data are read and written at the rising edges of the clock signals CLK.
Since a PDP that displays HD-level video has high resolution, it has a huge volume of video data to be processed. Since all the subfield data of one frame should be read and written within a single frame time, a frame memory clock having a frequency higher than that of the frame memory clock for SD-level video should be used to display HD-level video. Therefore, the clock frequency for displaying the HD-level video shown in FIG. 3B is higher than the clock frequency for an access to the frame memory when displaying SD-level video shown in FIG. 3A.
The video data of the full HD-level resolution 1,920×1,080 in the PDP is double that of the video data of the HD-level resolution 1,366×768, and hence, the clock frequency must be doubled to process the corresponding data within one frame time. When the clock frequency is doubled, no margins of a setup time and a hold time between the data and the clock signals exist during the process of writing/reading data to/from the frame memory, and therefore data can be lost. Also, when the clock frequency is doubled, calorific values of logic ICs increase, power consumption increases, circuit reliabilities worsen because of the increase of the calorific values, and the PDP lifespan is shortened.